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Features
* Low-voltage and Standard-voltage Operation * * * * * * * * * *
- VCC = 1.7V to 5.5V Internally Organized 256 x 8 (2K) Two-wire Serial Interface Schmitt Trigger, Filtered Inputs for Noise Suppression Bidirectional Data Transfer Protocol 1MHz (5V), 400kHz (1.7V, 2.5V, 2.7V) Compatibility Write Protect Pin for Hardware Data Protection 8-byte Page (2K) Write Modes Partial Page Writes Allowed Self-timed Write Cycle (5ms max) High-reliability - Endurance: 1 Million Write Cycles - Data Retention: 100 Years Green (Pb/Halide-free/RoHS Compliant) Package Options Die Sales: Wafer Form and Tape and Reel
* *
Two-wire Serial Electrically Erasable and Programmable Read-only Memory
2K (256 x 8)
Description
The Atmel(R) AT24C02C provides 2048-bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 256-words of 8-bits each. The device is optimized for use in many industrial and commercial applications where lowpower and low-voltage operation are essential. The AT24C02C is available in spacesaving 8-lead PDIP, 8-lead TSSOP, 8-lead JEDEC SOIC, 8-lead UDFN, 5-lead SOT23 and 8-ball VFBGA packages and is accessed via a two-wire serial interface. Table 0-1.
Pin Name A0 - A2 SDA SCL WP GND VCC Note:
Atmel AT24C02C
Pin Configuration
Function Address Inputs Serial Data Serial Clock Input Write Protect Ground Power Supply
A0 A1 A2 GND
8-lead PDIP
1 2 3 4 8 7 6 5 VCC WP SCL SDA A0 A1 A2 GND
8-lead SOIC
1 2 3 4 8 7 6 5 VCC WP SCL SDA
8-lead TSSOP
A0 A1 A2 GND 1 2 3 4 8 7 6 5 VCC WP SCL SDA
8-lead UDFN
VCC 8 WP 7 SCL 6 SDA 5 1 A0 2 A1 3 A2 4 GND
For use of 5-lead SOT23, the software A2, A1, and A0 bits in the device address word must be set to zero to properly communicate
Bottom View 5-lead SOT23
SCL GND SDA 1 2 3 4 VCC 5 WP
8-ball VFBGA
VCC 8 WP 7 SCL 6 SDA 5 1 A0 2 A1 3 A2 4 GND
Bottom View
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Absolute Maximum Ratings
Operating Temperature ........................-55C to +125C Storage Temperature ...........................-65C to +150C Voltage on Any Pin with Respect to Ground........................... -1.0V to +7.0V Maximum Operating Voltage................................. 6.25V DC Output Current .............................................. 5.0 mA *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Figure 0-1.
VCC GND WP SCL SDA
Block Diagram
START STOP LOGIC
LOAD DEVICE ADDRESS COMPARATOR A2 A1 A0 R/W COMP
SERIAL CONTROL LOGIC
EN
H.V. PUMP/TIMING
DATA RECOVERY INC X DEC EEPROM
LOAD
DATA WORD ADDR/COUNTER
Y DEC
SERIAL MUX
DIN DOUT
DOUT/ACK LOGIC
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Atmel AT24C02C
1. Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open-collector devices. DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that are hard wired for the Atmel(R) AT24C02C. As many as eight 2K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). WRITE PROTECT (WP): AT24C02C has a write protect pin that provides hardware data protection. The write protect pin allows normal read/write operations when connected to ground (GND). When the write protect pin is connected to VCC, the write protection feature is enabled and operates as shown in Table 1-1. Table 1-1.
WP Pin Status At VCC At GND
Write Protect
Part of the Array Protected Atmel 24C02C Full (2K) Array Normal Read/Write Operations
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2.
Memory Organization
Atmel AT24C02C, 2K SERIAL EEPROM: Internally organized with 32 pages of 8-bytes each, the 2K requires an 8-bit data word address for random word addressing.
Table 2-1. Pin Capacitance(1) Applicable over recommended operating range from TA = 25C, f = 1.0MHz, VCC = +1.7V to +5.5V
Symbol CI/O CIN Note: Test Condition Input/Output Capacitance (SDA) Input Capacitance (A0, A1, A2, SCL) 1. This parameter is characterized and is not 100% tested Max 8 6 Units pF pF Conditions VI/O = 0V VIN = 0V
Table 2-2. DC Characteristics Applicable over recommended operating range from: TAI = -40C to +85C, VCC = +1.7V to +5.5V (unless otherwise noted)
Symbol VCC1 VCC2 VCC3 VCC4 ICC ICC ISB1 ISB2 ISB3 ISB4 ILI ILO VIL VIH VOL2 VOL1 Note: Parameter Supply Voltage Supply Voltage Supply Voltage Supply Voltage Supply Current VCC = 5.0V Supply Current VCC = 5.0V Standby Current VCC = 1.7V Standby Current VCC = 2.5V Standby Current VCC = 2.7V Standby Current VCC = 5.0V Input Leakage Current Output Leakage Current Input Low Level(1) Input High Level
(1)
Test Condition
Min 1.7 2.5 2.7 4.5
Typ
Max 5.5 5.5 5.5 5.5
Units V V V V mA mA A A A A A A V V V V
READ at 100kHz WRITE at 100kHz VIN = VCC or VSS VIN = VCC or VSS VIN = VCC or VSS VIN = VCC or VSS VIN = VCC or VSS VOUT = VCC or VSS -0.6 VCC x 0.7 IOL = 2.1mA IOL = 0.15mA
0.4 2.0 0.6 1.4 1.6 8.0 0.10 0.05
1.0 3.0 3.0 4.0 4.0 18.0 3.0 3.0 VCC x 0.3 VCC + 0.5 0.4 0.2
Output Low Level VCC = 3.0V Output Low Level VCC = 1.7V
1. VIL min and VIH max are reference only and are not tested
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Atmel AT24C02C
Table 2-3. AC Characteristics Applicable over recommended operating range from TAI = -40C to +85C, VCC = +1.7V to +5.5V, CL = 1TTL Gate and 100pF (unless otherwise noted)
1.7, 2.5, 2.7 Symbol fSCL tLOW tHIGH tI tAA tBUF tHD.STA tSU.STA tHD.DAT tSU.DAT tR tF tSU.STO tDH tWR Endurance(1) Note: Parameter Clock Frequency, SCL Clock Pulse Width Low Clock Pulse Width High Noise Suppression Time Clock Low to Data Out Valid Time the bus must be free before a new transmission can start Start Hold Time Start Setup Time Data In Hold Time Data In Setup Time Inputs Rise Time Inputs Fall Time
(1)
5.0V Min Max 1000 0.4 0.4 Units kHz s s 50 0.05 0.5 0.25 0.25 0 100 0.55 ns s s s s s ns 0.3 100 .25 50 s ns s ns 5 1 Million ms Write Cycles
Min
Max 400
1.2 0.6 50 0.1 1.2 0.6 0.6 0 100 0.3 300 0.6 50 5 0.9
(1)
Stop Setup Time Data Out Hold Time Write Cycle Time 5.0V, 25C, Byte Mode
1. This parameter is ensured by characterization only
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3.
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see Figure 5-2 on page 8). Data changes during SCL high periods will indicate a start or stop condition as defined below. START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see Figure 5-3 on page 8). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 5-3 on page 8). ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle. STANDBY MODE: The Atmel(R) AT24C02C features a low-power standby mode which is enabled: (a) upon powerup and (b) after the receipt of the STOP bit and the completion of any internal operations. 2-Wire Software Reset: After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by following these steps: (a) Create a start bit condition, (b) clock 9 cycles, (c) create another start bit followed by stop bit condition as shown below. The device is ready for next communication after above steps have been completed. Figure 3-1. Software reset
Start bit Dummy Clock Cycles Start bit Stop bit
SCL
1
2
3
8
9
SDA
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4. Bus Timing
Figure 4-1. SCL: Serial Clock, SDA: Serial Data I/O
tF tHIGH tLOW tR
SCL
tSU.STA tHD.STA
tLOW
tHD.DAT
tSU.DAT
tSU.STO
SDA IN
tAA tDH tBUF
SDA OUT
5.
Write Cycle Timing
Figure 5-1. SCL: Serial Clock, SDA: Serial Data I/O
SCL
SDA
8th BIT
ACK
WORDn twr STOP CONDITION Notes:
(1)
START CONDITION
1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle
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Figure 5-2.
Data Validity
SDA
SCL DATA STABLE DATA CHANGE DATA STABLE
Figure 5-3.
Start and Stop Definition
SDA
SCL
START
STOP
Figure 5-4.
Output Acknowledge
SCL
1
8
9
DATA IN
DATA OUT
START
ACKNOWLEDGE
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6. Device Addressing
The 2K EEPROM device requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (refer to Figure 8-1). The device address word consists of a mandatory one, zero sequence for the first four most significant bits as shown. This is common to all the EEPROM devices. The next three bits are the A2, A1 and A0 device address bits for the 2K EEPROM. These three bits must compare to their corresponding hard-wired input pins. The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the chip will return to a standby state.
7.
Write Operations
BYTE WRITE: A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 8-2 on page 10). PAGE WRITE: The 2K EEPROM is capable of an 8-byte page write. A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to seven data words. The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 8-3 on page 10). The data word address lower three bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than eight data words are transmitted to the EEPROM, the data word address will "roll over" and previous data will be overwritten. ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a zero allowing the read or write sequence to continue.
8.
Read Operations
Read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. There are three read operations: current address read, random address read and sequential read. CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address "roll over" during read is from the last byte of the last memory page to the
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first byte of the first page. The address "roll over" during write is from the last byte of the current page to the first byte of the same page. Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input zero but does generate a following stop condition (see Figure 8-4 on page 11). RANDOM READ: A random read requires a "dummy" byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does generate a following stop condition (see Figure 8-5 on page 11). SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will "roll over" and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condition (see Figure 8-6 on page 11). Figure 8-1. Device Address
MSB
LSB
Figure 8-2.
Byte Write
Figure 8-3.
Page Write
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Figure 8-4. Current Address Read
Figure 8-5.
Random Read
Figure 8-6.
Sequential Read
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9.
Ordering Code Detail
AT24C02C-SSHM-B
Atmel Designator Shipping Carrier Option
B or blank = Bulk (tubes) T = Tape and Reel
Product Family
Operating Voltage
M = 1.7V to 5.5V
Device Density
02 = 2k
Package Device Grade or Wafer/Die Thickness
H = Green, NiPdAu lead finish, Industrial Temperature Range (-40C to +85C) U = Green, matte Sn lead finish, Industrial Temperature range (-40C to +85C) 11 = 11mil wafer thickness
Device Revision
Package Option
P = PDIP SS = JEDEC SOIC X = TSSOP MA = UDFN ST = SOT23 C = VFBGA WWU = Wafer unsawn WDT = Die in Tape and Reel
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10. Part Markings
Atmel AT24C02C-PUM
Top Mark Seal Year | Seal Week | | | |---|---|---|---|---|---|---|---| A T M L U Y W W |---|---|---|---|---|---|---|---| 0 2 C M @ |---|---|---|---|---|---|---|---| * LOT NUMBER |---|---|---|---|---|---|---|---| | PIN 1 INDICATOR (DOT)
U= Y= WW = 02C= @= M= *Lot
Material Set Seal Year Seal Week Device Country of Assembly Voltage Indicator Number to Use ALL Characters in Marking
BOTTOM MARK No Bottom Mark
Atmel AT24C02C-SSHM
Top Mark Seal Year | Seal Week | | | |---|---|---|---|---|---|---|---| A T M L H Y W W |---|---|---|---|---|---|---|---| 0 2 C M @ |---|---|---|---|---|---|---|---| * LOT NUMBER |---|---|---|---|---|---|---|---| | PIN 1 INDICATOR (DOT)
H= Y= WW = 02C= M= @= *Lot
Material Set Seal Year Seal Week Device Voltage Indicator Country of Assembly Number to Use ALL Characters in Marking
BOTTOM MARK No Bottom Mark
Atmel AT24C02C-XHM
Top Mark PIN 1 INDICATOR (DOT) | |---|---|---|---|---|---| * A T H Y W W |---|---|---|---|---|---| 0 2 C M @ |---|---|---|---|---|---| ATMEL LOT NUMBER |---|---|---|---|---|---|---|
H= Y= WW = 02C= M= @=
Material Set Seal Year Seal Week Device Voltage Indicator Country of Assembly
BOTTOM MARK No Bottom Mark
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Atmel AT24C02C-MAHM
Top Mark |---|---|---| 0 2 C |---|---|---| H M @ |---|---|---| Y T C |---|---|---| * | PIN 1 INDICATOR (DOT) 02C= H= M= @= Y= TC = Device Material Set Voltage Indicator Country of Assembly Year of Assembly Trace Code
Atmel AT24C02C-STUM
Top Mark |---|---|---|---|---| 2 C M B U |---|---|---|---|---| * | PIN 1 INDICATOR (DOT) 2C M B U = = = = Device Voltage Indicator Write Protection Material Set
Line 1 -------->
Bottom Mark |---|---|---|---| Y M T C |---|---|---|---| Y = One Digit Year Code M = Seal Month TC = Trace Code
Atmel AT24C02C-CUM
Top Mark 02C= U= Y= M= TC = Device Material Set One Digit Year Code Seal Month Trace Code
Line 1 -------> 02CU Line 2 -------> YMTC |<--PIN 1 THIS CORNER
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11. Ordering Codes
Atmel AT24C02C Ordering Information
Ordering Code AT24C02C-PUM (Bulk form only) AT24C02C-SSHM-B AT24C02C-XHM-B
(1)
Voltage 1.7V to 5.5V 1.7V to 5.5V 1.7V to 5.5V 1.7V to 5.5V 1.7V to 5.5V 1.7V to 5.5V 1.7V to 5.5V 1.7V to 5.5V 1.7V to 5.5V (NiPdAu Lead Finish)
Package 8P3 8S1 8S1 8A2 8A2 8Y6 5TS1 8U3-1 Die Sale
Operation Range
AT24C02C-SSHM-T(2) (NiPdAu Lead Finish)
(1)
(NiPdAu Lead Finish) (NiPdAu Lead Finish)
AT24C02C-XHM-T(2) (NiPdAu Lead Finish) AT24C02C-MAHM-T
(2)
Lead-free/Halogen-free/ Industrial Temperature (-40C to 85C)
AT24C02C-STUM-T(2) AT24C02C-CUM-T(2) AT24C02C-WWU11(3) Notes: 1. "-B" denotes bulk
Industrial Temperature (-40C to 85C)
2. "-T" denotes tape and reel. SOIC = 4K per reel. TSSOP, UDFN, SOT23, and VFBGA = 5K per reel 3. For Wafer sales, please contact Atmel Sales
Package Type 8P3 8S1 8A2 8Y6 5TS1 8U3-1 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8-lead, 4.4mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) 8-lead, 2.00mm x 3.00mm Body, 0.50mm Pitch, Dual No Lead Package (UDFN) 5-lead, 2.90mm x 1.60mm Body, Plastic Thin Shrink Small Outline Package (SOT23) 8-ball, die Ball Grid Array Package (VFBGA)
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12.
Packaging Information
8P3 - PDIP
1
E E1
N
Top View
c eA
End View
COMMON DIMENSIONS (Unit of Measure = inches)
D D1
e A2 A
SYMBOL
MIN
NOM
MAX
NOTE
A A2 b b2 b3 c D 0.115 0.014 0.045 0.030 0.008 0.355 0.005 0.300 0.240 0.310 0.250 0.100 BSC 0.300 BSC 0.115 0.130 0.130 0.018 0.060 0.039 0.010 0.365
0.210 0.195 0.022 0.070 0.045 0.014 0.400 0.325 0.280
2 5 6 6 3 3 4 3 4
b2 b3
4 PLCS
L
D1 E E1 e eA L
b
Side View
0.150
2
Notes:
1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25mm).
07/19/10 TITLE GPC DRAWING NO. 8P3 REV. C
Package Drawing Contact: 8P3, 8-lead, 0.300" Wide Body, Plastic Dual packagedrawings@atmel.com In-line Package (PDIP)
PTC
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Atmel AT24C02C
8S1 - JEDEC SOIC
C
1
E
E1
N
L
O
TOP VIEW END VIEW
e b A A1
SYMBOL A A1 b C COMMON DIMENSIONS (Unit of Measure = mm) MIN 1.35 0.10 0.31 0.17 4.80 3.81 5.79 NOM - - - - - - - 1.27 BSC 0.40 0 - - 1.27 8 MAX 1.75 0.25 0.51 0.25 5.05 3.99 6.20 NOTE
D
D E1
SIDE VIEW
Notes: This drawing is for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
E e L
O
5/19/10 TITLE GPC DRAWING NO. 8S1 REV. F
Package Drawing Contact: 8S1, 8-lead (0.150" Wide Body), Plastic Gull packagedrawings@atmel.com Wing Small Outline (JEDEC SOIC)
SWB
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8A2 - TSSOP
3
21
Pin 1 indicator this corner
E1
E
L1
N L
Top View
End View
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL D MIN 2.90 NOM 3.00 6.40 BSC 4.30 - 0.80 0.19 4.40 - 1.00 - 0.65 BSC 0.45 0.60 1.00 REF 0.75 4.50 1.20 1.05 0.30 4 3, 5 MAX 3.10 NOTE 2, 5
b
A
E E1 A
e D
A2
A2 b e L L1
Side View
Notes:
1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15mm (0.006in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25mm (0.010in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07mm. 5. Dimension D and E1 to be determined at Datum Plane H. 5/19/10
TITLE
GPC
DRAWING NO. 8A2
REV. E
Package Drawing Contact: 8A2, 8-lead 4.4mm Body, Plastic Thin packagedrawings@atmel.com Shrink Small Outline Package (TSSOP)
TNR
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8Y6 - UDFN
D2
A
b (8X)
Pin 1 Index Area E2 E
Pin 1 ID L (8X)
D A2 A3 A1
e (6X) 1.50 REF.
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE
D E Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-229, for proper dimensions, tolerances, datums, etc. 2. Dimension b applies to metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area. 3. Soldering the large thermal pad is optional, but not recommended. No electrical connection is accomplished to the device through this pad, so if soldered it should be tied to ground D2 E2 A A1 A2 A3 L e b 0.20 0.20 1.40 - - 0.00 -
2.00 BSC 3.00 BSC 1.50 - - 0.02 - 0.20 REF 0.30 0.50 BSC 0.25 0.30 2
11/21/08
1.60 1.40 0.60 0.05 0.55 0.40
TITLE
GPC
DRAWING NO.
REV.
8Y6, 8-lead, 2.0x3.0mm Body, 0.50mm Pitch, Package Drawing Contact: packagedrawings@atmel.com UltraThin Mini-MAP, Dual No Lead Package (Sawn)(UDFN)
YNZ
8Y6
E
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5TS1 - SOT23
e1
5 4
C
E1
E
C L
L1
1 2 3
Top View
b
End View
A2
SEATING PLANE
A
e D
A1
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE
Side View
Notes: 1. Dimensions D does not include mold flash, protrusions or gate burrs. Mold flash protrusions or gate burrs shall not exceed 0.15mm per end. Dimensions E1 does not include interlead flash or protrusion. Interlead flasg or protrusion shall not exceed 0.15mm per side. 2. The package top may be smaller than the package bottom. Dimensions D and E1 are deteremined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs, and interlead flash, but including any mismatch between the top and bottom of the plastic body. 3. These dimensions apply to the flat section of the lead between 0.08mm and 0.15mm from the lead tip. 4. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.80mm total in excess of the "b" dimension at maximum material condition. The dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and an adjacent lead shall not be less than 0.07mm. 5. This drawing is for general information only. Refer to JEDEC Drawing MO-193, Variation AB for additional information.
A A1 A2 c D E E1 L1 e e1 b
- 0.00 0.70 0.08
- - 0.90 - 2.90 BSC 2.80 BSC 1.60 BSC 0.60 REF 0.95 BSC 1.90 BSC
1.10 0.10 1.00 0.20 3 1, 2 1, 2 1, 2
0.30
-
0.50
3, 4
11/05/08
TITLE
GPC
DRAWING NO.
REV.
5TS1, 5-lead, 1.60mm Body, Plastic Thin Package Drawing Contact: packagedrawings@atmel.com Shrink Small Outline Package (Shrink SOT)
TSZ
5TS1
B
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8U3-1 - VFBGA
E
D 5. b
PIN 1 BALL PAD CORNER A2
A1
TOP VIEW
PIN 1 BALL PAD CORNER 1 2 3 4
A
SIDE VIEW
d
(d1) 8 7 6 e (e1) 5
COMMON DIMENSIONS (Unit of Measure - mm) SYMBOL A A1 A2 MIN 0.73 0.09 0.40 0.20 NOM 0.79 0.14 0.45 0.25 1.50 BSC 2.0 BSC 0.50 BSC 0.25 REF 1.00 BSC 0.25 REF MAX 0.85 0.19 0.50 0.30 2 NOTE
BOTTOM VIEW
8 SOLDER BALLS
Notes:
1. This drawing is for general information only. 2. Dimension `b' is measured at maximum solder ball diameter. 3. Solder ball composition shall be 95.5Sn-4.0Ag-.5Cu.
b D E e e1 d d1
07/14/10 TITLE GPC DRAWING NO. 8U3-1 REV. D
Package Drawing Contact: 8U3-1, 8-ball, 1.50 x 2.00mm Body, packagedrawings@atmel.com 0.50 pitch, VFBGA Package (dBGA2)
GXU
21
8700D-SEEPR-8/10
13.
Revision History
Doc. Rev. 8700D Date 08/2010 Comments Changed AT24C02C-XHM Part Marking from C02CM@ to 02CM @ Ordering Information: - Changed Atmel AT24C02C-TSUM-T to Atmel AT24C02C-STUM-T - Changed Atmel AT24C02CY6-MAHM-T to Atmel AT24C02C-MAHM-T - Changed Atmel AT24C02CU3-CUM-T to Atmel AT24C02C-CUM-T Catalog Numbering Scheme, changed TS = SOT23 to ST = SOT23 Part Marking SOT23: - Changed 2CMWU to 2CMBU - Changed W = Write Protection Feature to B = Write Protection Part Marking PDIP and SOIC: Added @ = Country of Assembly Part Marking TSSOP: Replaced and removed bottom mark Part Marking UDFN: Added HM@ Remove Preliminary Status Changed tI Max 40 to 50 in Table AC Characteristics Corrected Catalog Numbering Scheme and Ordering Information Initial Document Release
8700C
07/2010
8700B 8700A
02/2010 12/2009
22
Atmel AT24C02C
8700D-SEEPR-8/10
Headquarters
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Technical Support s_eeprom@atmel.com Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature
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8700D-SEEPR-8/10

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